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Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1402 is pin compatible with the MAX1632 with improved load regulation performance. The SC1402 is a multiple-output power supply controller designed to power logic supply components in battery operated systems. The SC1402 utilizes synchronous rectified buck topologies to generate two voltages, (3.3V and 5V) with up to 95% efficiency. It also provides two linear regulators for system housekeeping functions. The 12V linear regulator output is generated from a coupled inductor of the 5V switching regulator. Control functions include: power up sequencing, soft start, power-good signaling, automatic bootstrapping for high side MOSFETs, and frequency synchronization. An internal precision 2.5V reference ensures 2% output voltage. The internal oscillator can be adjusted to 200kHz, 300kHz or synchronized to an external clock. The MOSFET drivers provide 1A peak drive current for fast MOSFET switching. The SC1402 includes a PSAVE enable input to select a pulse skipping mode for high efficiency or a fixed frequency mode for low noise operation.
FEATURES *= 6V to 30V Input range *= 3.3V and 5V dual synchronous rectified outputs *= Fixed frequency or PSAVE for maximum efficiency *= *= *= *= *= *= *= *= *= *=
over wide load current range 5V/50mA linear regulator 12V/120mA linear regulator Precision 2.5V reference output Programmable power-up sequence Power good output (RESET) Output over current protection Output over voltage protection Output under voltage shut down 4A typical shut down current 7mW typical quiescent power
APPLICATIONS *= Notebook and subnotebook computers *= PDAs and Mobile communicators *= Desktop DC-DC converters ORDERING INFORMATION:
DEVICE SC1402ISS PACKAGE
(1)
TEMP. (TA) -40 - +85C
SSOP-28
TYPICAL APPLICATION CIRCUIT
Note: (1) Only available in tape and reel packaging. (Suffix `.TR').
1 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
ABSOLUTE MAXIMUM RATINGS
PARAMETERS V+, BST3, BST5 to GND PGND to GND PHASE3 to BST3, and PHASE5 to BST5 VL to GND REF,SYNC,SEQ,PSAVE,TIME_ON5,RESET to GND RUN/ON3, SHDN to GND VDD to GND 12 Out to GND VL, REF Short to GND 12 Out Short to GND REF Current VL Current 12 Out Current VDD Shunt Current TS Storage Temperature TL Lead soldering temperature MAXIMUM -0.3, +36 0.3 -6 to +0.3 -0.3 to 6 -0.3 to (VL+.3V) -0.3 to (V+ + 0.3V) -0.3 to +30V -0.3 to (VDD + 0.3V) Continuous Continuous +5 +50 +200 +15 -65 to +150 +300, 10 seconds UNITS V V V V V V V V sec. sec. mA mA mA mA C C
ELECTRICAL CHARACTERISTICS
(1)
(Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA =-40 to +85C. Typical values are at TA = +25C).
PARAMETER CONDITIONS MAIN SMPS CONTROLLERS Input Voltage Range 3V Output Voltage in V+ = 6V to 30V, CSH3-CSL3 = 0V, Adjustable Mode CSL3 tied to FB3 3V Output Voltage in Fixed Mode V+ = 6V to 30V, 0mV < CSH3-CSL3 < 80mV, FB3 = 0V 5V Output Voltage in Adjustable V+ = 6V to 30V, CSH5-CSL5 = 0V, Mode CSL5 tied to FB5 5V Output Voltage in Fixed Mode V+ = 6V to 30V, 0mV < CSH5-CSL5 < 80mV, FB5 = 0V Output Voltage Adjust Range Either SMPS Adjustable-Mode Threshold Dual Mode comparator Voltage Load Regulation Either SMPS, 0V < CSH_-CSL_ < 80mV Line Regulation Current-Limit Threshold PSAVE Mode Threshold Soft-Start Ramp Time Oscillator Frequency Maximum Duty Factor Either SMPS, 6V < V+ < 30V CSH3-CSL3 or CSH5-CSL5 PSAVE = VL or V12OUT < 11.9V PSAVE = 0V, not tested From enable to 95% full current limit with respect to fOSC Note 2. SYNC = VL SYNC = 0V SYNC = VL SYNC = 0V
MIN 6.0 2.45 3.17 2.45 4.82 REF 0.5
TYP
MAX 30.0 2.55 3.43 2.55 5.18 5.5 1.3
UNITS V V V V V V V % %/V
2.5 3.3 2.5 5.0
-0.8 80 -50 10 0.03 100 -100 25 512 270 170 300 200 94 96 330 235 120 -150 40
mV mV clks kHz % 2
(c) 2000 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
ELECTRICAL CHARACTERISTICS (continued)
(Unless otherwise noted: (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA = -40 to +85C Typical values are at TA = +25C).
PARAMETER SYNC Input High Pulse SYNC Rise/Fall Time
2 2 2
CONDITIONS
MIN 300 300
TYP
MAX UNITS ns 200 350 kHz A
SYNC Input Low Pulse Width
SYNC Input Frequency Range Current-Sense Input Leakage Current FLYBACK CONTROLLER VDD Shunt Threshold VDD Shunt Sink Current VDD Leakage Current 12V LINEAR REGULATOR 12OUT Output Voltage 12OUT Current Limit 12OUT Regulation Threshold Quiescent VDD Current VL Output Voltage Undervoltage Fault Lockout Threshold Switchover Threshold REF Output Voltage REF Load Regulation REF Sink Current REF Fault Lockout Voltage V+ Operating Supply Current V+ Standby Supply Current V+ Shutdown Supply Current Quiescent Power Consumption Falling edge VL switched over to CSL5, 5V SMPS on V+ = 6V to 30V, SMPS off, includes current into SHDN V+ = 6V to 30V, SHDN = 0V SMPS enabled, FB3 = FB5 = 0V, CSL3 = CSH 3 = 3.5V, CSL5 = CSH5 = 5.5V 0mA < Load < 120mA 12OUT forced to 11V, VDD = 13V Falling edge VDD = 18V, run mode, no 12OUT load SHDN = V+, 6V < V+ < 30V, 0mA < ILOAD < 50mA, RUN/ON3 = TIME/ON5 = 0V Falling edge, hysteresis = 0.9V Switch over at startup No external load, Standby Mode 0A < LOAD < 50A 0mA < LOAD < 5mA Rising edge, hysteresis = 1% VDD = 20V VDD = 5V , Standby mode V+ = VL = 0V, CSL3 = CSH3 = CSL5 = CSH5 = 5.5V
240 0.01
10
18 5 10
20 30 30
V mA A V mA V
11.55
12.1 12.50 150 11.9 50 100 5.2 3.7 4.5 4.0
A
INTERNAL REGULATOR AND REFERENCE 4.6 3.5
V 2.45 2.5 2.55 12.5 50 10 1.8 10 180 A 4 7.5 20 mW 2.2 50 A V mV
Table 2
3 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
ELECTRICAL CHARACTERISTICS (continued)
(Unless otherwise noted: (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA = -40 to +85C Typical values are at TA = +25C).
PARAMETER FAULT DETECTION Overvoltage Trip Threshold Overvoltage-Fault Propagation Delay Output Undervoltage Threshold Output Undervoltage Lockout Time Thermal Shutdown Threshold RESET RESET Trip Threshold RESET Propagation Delay RESET Delay Time INPUTS AND OUTPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Logic Output Low Voltage Logic Output High Current TIME/ON5 Input Trip Level TIME/ON5 Source Current TIME/ON5 On-Resistance Gate Driver Sink/Source Current Gate Driver On-Resistance
CONDITIONS With respect to unloaded output voltage CSL_ driven 2% above overvoltage trip threshold With respect to unloaded output voltage From each SMPS enabled, with respect to fOSC Typical hysteresis = +10C
MIN 3.5
TYP 7 1.5
MAX 10
UNITS % s
60 5000
70 6144 150
80 7000
% clks C
With respect to unloaded output voltage, falling edge; typical hysteresis = 1% Falling edge, CSL_ driven 2% below RESET trip threshold With respect to fOSC RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHDN, SYNC RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHDN, SYNC RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHDN, SYNC, SEQ = 0V or 3.3V RESET, ISINK = 4mA RESET = 3.5V SEQ = 0 or VL TIME/ON5 = 0V, SEQ = 0 or VL TIME/ON5, RUN/ON3 = 0V, SEQ = 0 or VL DL3, DH3, DL5, DH5, forced to 2V High or low
-10
-7 1.5
-4
% s clks V V
27,000 32,000 37,000
0.6 2.4 +1 0.4 1 2.4 2 3 100 1 1.5 7 2.6 4
A V mA V A A
Note 1: This device is ESD sensitive. Use of standard ESD handling precautions is required. Note 2: Guaranteed by design.
4 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
BLOCK DIAGRAM
VL
5 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
Top View
SSOP-28
PWM CONTROLLER DIAGRAM (Fig. 1)
6 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
PIN DESCRIPTION
Pin # Pin Name
1 2 3 CSH3 CSL3 FB3
Pin Function
Current Sense Input for the 3.3V SMPS. Current limit level is 100mV referred to CSL3. Current Sense Input. Also serves as the feedback input in fixed output mode. Feedback Input for the 3.3V SMPS; Connect FB3 to a resistor divider for adjustable output mode and FB3 is regulated to REF (approx. 2.5V). FB3 selects the 3.3V fixed output voltage setting when tied to GND. 12V, 120mA Linear Regulator Output. Input supply comes from VDD. Bypass 12 OUT to GND with 1F minimum capacitor. Supply Voltage Input for the 12 OUT Linear Regulator. Also connects to a 18V overvoltage shunt regulator clamp. Oscillator Synchronization and Frequency Select. Tie to VL for 300kHz operation; tie to GND for 200kHz. Driven externally to SYNC between 240kHz and 350kHz. Dual Purpose Timing Capacitor Pin and 5V SMPS ON/OFF Control Input. Input resistor of 1K is required when using ON/OFF control input. Low noise Analog Ground and Feedback reference point. 2.5V Reference Voltage Output. Bypass to GND with 1F minimum capacitor. Logic Control Input that disables PSAVE Mode when high. Connect to GND for power save mode. Active Low Timed Output. RESET swings from GND to VL. Goes high after 32,000 clock cycle delay following power up as a power good signal. Feedback Input for 5V SMPS; Connect FB5 to a resistor divider for adjustable output mode and FB5 regulates to REF (approx. 2.5V). FB5 selects the 5V fixed output voltage setting when tied to GND. Current Sense Input for 5V SMPS. Current Sense Input for 5V SMPS. Input that selects SMPS power up sequence. Gate Drive Output for the 5V, high side N-Channel MOSFET. Switching Node inductor connection. Boost capacitor connection for 5V, SMPS high-side gate drive. Connect a 0.1F capacitor. Gate Drive Output for the 5V, SMPS low-side N-Channel MOSFET. Power Ground. 5V, Internal Linear Regulator Output. Battery Voltage Input. Shutdown Control Input, active low. Gate Drive Output for the 3.3V, SMPS low-side N-Channel MOSFET. Boost Capacitor Connection for high side gate drive. Connect a 0.1F capacitor. Switching Node inductor Connection. Gate Drive Output for the 3.3V, high-side N-Channel MOSFET. ON/OFF Control Input of 3.3V SMPS.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
12 OUT VDD SYNC TIME/ON5 GND REF PSAVE RESET FB5 CSL5 CSH5 SEQ DH5 PHASE5 BST5 DL5 PGND VL V+ SHDN DL3 BST3 PHASE3 DH3 RUN/ON3
Note: All logic level inputs and outputs are open collector TTL compatible.
7 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
Detailed Description
The SC1402 is a multiple-output, high efficiency, versatile power supply controller designed to power battery operated systems. Four high current gate drive outputs are supplied to control all MOSFETs in two synchronous rectified buck converters. These buck converters can be programmed to operate at either fixed or adjustable output voltages. The power save feature of the SC1402 achieves high efficiency over a wide range of load current. The control and fault monitoring circuitry associated with each PWM controller includes digital softstart, turn-on sequencing, voltage error amplifier with slope compensation, pulse width modulator, power save, over-current and over-voltage and under voltage fault protection. Two linear regulators and a precision reference voltage are also provided by the SC1402.
until the beginning of the next switching cycle. Again, active shoot-through protection ensures that the gate to the low-side MOSFET has dropped low before the high side MOSFET is turned on. When PSAVE is enabled (low) and the output current drops below 25% of its peak level, the PWM logic will automatically enter PSAVE mode to improve efficiency. When the controller enters power save, it increases the regulation point by 0.8%, typically issuing one more high side pulse as the converter enters PSAVE. The PWM control then disables switching cycles until the FB falls below the reference. At light loads the effective switching frequency will drop dramatically and efficiency will increase because of the reduced gate charge current required to switch the power stage. Boosting the regulation point when entering PSAVE gives the output improved dynamic regulation because the output voltage is not allowed to droop below the nominal regulation point. Load current steps, that cause the converter to come out of PSAVE, will not cause as large a negative dip in the output voltage.
PWM Control Block
The two PWM control blocks for the 3V and 5V power supply outputs are identical. The SC1402 employs peak current mode control with slope compensation to provide fast output response to load and line transients. The PWM control block consists of an analog PWM modulator followed by PWM logic control. The analog modulator combines the output current, slope compensation signal and error voltage to generate a PWM pulse train. The PWM logic uses the pulse train from the modulator and other control signals to generate the output states for the high and low side gate driver outputs. A block diagram of the PWM control block is shown in Fig. 1. An error amplifier generates the difference signal between the reference voltage and the feedback voltage to generate the error voltage for the peak current mode comparator. A nominal gain of 8 is used in the error amplifier to increase the system loop gain and to reduce the load regulation error typically seen in low loop-gain, current-mode controllers. The increased gain in the voltage loop is compensated by pole-zeropole response of the voltage error amplifier. The current feedback signal is summed with the slope compensation signal and compared to the error voltage at the PWM comparator. When the power supply is operating in continuous conduction mode, the high-side MOSFET is turned on at the beginning of each switching cycle. The high-side MOSFET is turned off when the desired duty cycle is reached. Active shoot-thruough protection delays the turn-on of the low-side MOSFET until the phase node drops below 2.5V. The low-side MOSFET remains on
Gate Drive/Control
The gate driver on the SC1402 are designed to switch large MOSFETs up to 350kHz. The high side gate driver is required to drive the gates of the high side MOSFET above the V+ input. The supply for the gate driver is generated by charging a bootstrap capacitor from the VL supply when the low-side driver is on. Monitoring circuit ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. In continuos conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side driver is off. Under light load conditions the inductor ripple current will approach the point where it reverses polarity. This is detected by the low side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. The low-side driver operation is also affected by various fault conditions as described in the Fault Protection section.
Internal Bias Supply
The VL linear regulator provides a 5V output that is used to power the gate drivers, 2.5V reference, and internal control sections of the SC1402. The regulator is capable of supplying up to 50mA (including MOS-
8 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000 FET gate charge current). The VL pin should be bypassed to GND with 4.7uF to supply the peak current requirements of the gate driver outputs. This regulator receives its input power from the V+ battery input. Efficiency is improved by providing a bootstrapping mode for the VL bias. When the 5V SMPS output voltage reaches 5V, internal circuitry detects this condition and turns on a PMOS pass device between CSL5 and VL. The internal VL regulator is then disabled and the VL bias is provided by the high efficiency switch mode power supply. The REF output is accurate to +/- 2% over temperature. It is capable of delivering 5mA max and should be bypassed with 1uF minimum capacitor. Loading the REF output will reduce the REF voltage slightly.
SC1402
If either SMPS output is greater than 7% above its nominal value, both SMPS are latched off and synchronous rectifiers are latched on. To prevent the output from ringing below, ground a 1A Schottky diode should be placed across each output, anode at GND. Two different levels of undervoltage are detected. If the output falls 5% below its nominal output, the RESET output is pulled low. If the output falls 30% below its nominal output following a startup delay, both SMPS are latched off. Both of the latched fault modes will remain in effect until SHDN or RUN/ON3 is toggled or the V+ input is brought below 1V.
Shutdown and Operating Modes
Holding the SHDN pin low disables the SC1402, reducing the V+ input current to <10uA. When SHDN goes high, the part enters a standby mode where the VL regulator and VREF are enabled. Turning on either SMPS will put the SC1402 in run mode. SHDN RUN/ ON3 X TIME/ ON5 X MODE DESCRIPTION
Current Sense (CSH,CSL)
The output current of the power supply is sensed as the voltage drop across an external resistor between the CSH and CSL pins. Over-current is detected when the current sense voltage exceeds +/-100mV. The negative current limit (i.e. -100mV) is required for operation with PSAVE mode disabled, and also to limit the output current when charging the bulk supply capacitor of the 12V regulator. A positive over-current will turn off the high-side driver, a negative over-current will turn off the low-side driver, each on a cycle by cycle basis. The current sense is also used for peak current feed back in the main PWM loop and for determining the current level for entering power save mode and the turn off time for the synchronous rectifier.
Low
Shutdown Standby
Minimum bias current VREF and VL regulator enabled Both SMPS Running
High
Low
Low
Oscillator
The SC1402 oscillator frequency is trimmed to +/10%. When the SYNC pin is set high the oscillator runs at 300kHz; when SYNC is set low the frequency is 200kHz. The oscillator can also be synchronized to the falling edge of a clock on the SYNC pin with a frequency between 240kHz and 350kHz. In general, 200kHz operation is used for highest efficiency, and the 300kHz for minimum output ripple and/or smaller inductor and output capacitor sizes. High High High Run Mode
Output Voltage Selection
If FB is connected to ground, internal resistors setup 3.3V and 5V output voltages. If external resistors are used, the internal feedback is disabled and the output is regulated based on 2.5V at the FB pin.
Fault Protection
In addition to cycle-by-cycle current limit, the SC1402 monitors over-temperature, and output over-voltage and under-voltage conditions. The over-temperature detect will shut the part down if the die temperature exceeds 150C with 10C of hysteresis.
12OUT Supply
The 12OUT linear regulator is capable of supplying 120mA. The input voltage to the 12OUT regulator is generated by a secondary winding on the 5V SMPS
9 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000 inductor. A heavy load on the 12OUT regulator when the 5V SMPS is in PSAVE will cause the VDD input to drop, browning out the regulator. If the output drops 0.8% from its nominal value, the 5V SMPS is forced out of PSAVE mode and into continuous conduction mode for 8 cycles. This recharges the bulk input capacitor on VDD. The 12OUT linear regulator has a current limit to prevent damage under short circuit conditions. Over-voltage protection is provided on the VDD input. If the VDD input is above 19V, an over-voltage is detected and a 10mA current shunt load is applied to VDD. The over-voltage threshold has 0.5V of hysteresis.
SC1402
Each SMPS contains its own counter and DAC to gradually increase the current limit at startup to prevent input surge currents. The current limit is increased from 0, 20%, 40%, 60%, 80%, to 100% linearly over the course of 512 switching cycles. A RESET output is also generated at startup. The RESET pin is held low for 32K switching cycles. Another timer is used to enable the undervoltage protection. The undervoltage protection circuitry is enabled after 6144 switching cycles at which time the SMPS should be in regulation. When SEQ is set to REF, the RESET only monitors the 3.3V SMPS in regulation. The 5V SMPS is ignored.
Power up Controls and Soft Start
The user has control of the SC1402 startup sequence by setting the SEQ, RUN/ON3 and TIME/ON5 pins as described in the following table.
SEQ REF REF REF REF GND GND VL VL
RUN/ON3 LOW LOW HIGH HIGH LOW HIGH LOW HIGH
TIME/ON5 LOW HIGH LOW HIGH TIMING CAP TIMING CAP TIMING CAP TIMING CAP
RESET Follows 3.3V SMPS. Low. Follows 3.3V SMPS. Follows 3.3V SMPS. Low. High after both outputs are in regulation. Low. High after both outputs are in regulation.
DESCRIPTION Independent start control mode. Both SMPSs off. 5V SMPS ON, 3.3V SMPS OFF. 3.3V SMPS ON, 5V SMPS OFF. Both SMPSs on. Both SMPS off. 5V starts on rising edge of RUN/ON3, 3V starts when TIME/ON5 > REF. Both SMPS off. 3.3V starts on rising edge of RUN/ON3, 5V starts when TIME/ON5 > REF.
10 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
APPLICATION INFORMATION
Introduction The SC1402 is a versatile dual switching regulator adjustable from 2.5V to 5.5V with fixed 5V and 3.3V modes. In addition, there are two on-chip 12V & 5V linear regulators capable of supplying 120mA & 50mA of output current, respectively. The SC1402 is designed for notebook applications but has applications anywhere high efficiency, small size and low cost are required. The Semtech SC1402 EVAL board consists of a 3.3V, 3A switcher, a 5.0V, 3A switcher, an onboard 12V linear regulator. A 15V flyback supply developed off the 5V SMPS inductor delivers the input voltage to the onboard 12V linear regulator. Design Guidelines The schematic for the EVAL board is shown on page 18. The EVAL board is configured as follows: Switching Regulator 1 Switching Regulator 2 Linear Regulator 1 Linear Regulator 2 Designing the Output Filter Before calculating the output filter inductance and output capacitor, an acceptable amount of output ripple current is to be determined. The ESR of the output capacitor multiplied by the ripple current sets the maximum allowable ripple voltage. So once the ripple voltage specification is selected, the capacitor ESR is chosen usually based on capacitor cost and size constraints. This then sets the maximum output ripple current through the capacitor and inductor. For the EVAL board 3.3V switcher, we selected a maximum ripple voltage of 50mV. Choosing two 330uF, 6.3V tantalum capacitors C21 & C22, each having an ESR of 100m, their combined ESR equaling 50m, sets the maximum ripple current as follows: Vout1 = 3.3V, 3A Vout2 = 5.0V, 3A Vout3 = 12V, 120mA Vout4 = 5V, 50mA
Be sure that the two output capacitors can handle this ripple current. Ripple current specifications are found in the capacitor data sheet for high quality capacitors intended for use in switching power supplies. The inductance can now be found:
L1 = (VINMAX - VO ) * D * t IO
These inductance and duty cycle equations exclude any resistive drops due to winding resistance and MOSFET on resistance. Where: For f = 300KHz, t = 1/f
(28 - 3.3) * 3.3 * 3.33 * 10 - 6 28 1
V D = O ; L1 = VIN
From this calculation we choose L1 to be 10uH. For a 200kHz operating frequency, L1 calculates to be 14.5uH. Choosing Inductor & FET Current Rating The current carrying capability of the inductor and MOSFETs should be sized to handle the maximum current of the supply set by the current sense resistor, Rsense = R9. Here we use the minimum current threshold value:
R9 = 80mV IPEAK
Where Ipeak equals:
IPEAK = IOUT + IO 2
Ipeak = 3.5 Amps
R9 = 0.080 = 0.023 3.5
Here we chose a sense resistor of 20m. Now we can determine FET and inductor current carrying capability
IO =
VO ESR
IO =
0.05 = 1Amp 0.05
11 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000 by using the maximum current limit threshold:
I PEAK = 0.120 R9 = 0.120 0.020 =6
SC1402
Step 2: Determine the Maximum & Minimum ESR Capacitance
ESRmax =
From this value choose an inductor with Isat > 6 Amps, and for the FET choose a continuous conduction current rating greater than 6 Amps. The same calculation process can be made for the 5V supply for its Inductor L2 and Rsense resistor, R8. The results are: L2 = 13.4 uH at 300KHz, 20uH at 200KHz, For our EVAL board we choose the transformer with a 11uH primary at the expense of slightly higher ripple current. R8 = 0.02 Co = C18 = 330uF/10V Calculating output capacitance and ESR for Stability. Now that the basic output filter has been designed, it is time to check if the output filter will allow stable operation. Since the control loop is internal to the SC1402, the output filter capacitor and its associated equivilant series resistance (ESR), will effect stability. It is important to choose a capacitor with its ESR for stable SMPS operation. A seven step procedure for choosing the output capacitor and ESR ensuring a stable control loop is shown below for the 3.3V supply. The same procedure should also be implemented for the 5V supply. System Paramaters: Fs = 300000Hz Vout = 3.3V Vref = 2.5V Rs = 0.020 Vinmin = 6V
Vout * Rs Vref
ESRmax = 0.026
ESRmin =
ESRmax
(1.2)2
ESRmin= 0.018
Step 3: Determine the Minimum Output Capacitance
Comin =
Vref 2 * * Fc * Vout * Rs * tan 30 0
()
Comin = 162uF
Step 4: Determine the Actual Output Capacitance
Co =
ESRmax * Comin ESRmin
Co = 233uF
Step 5: Determine the Actual ESR Value
ESR =
ESRmax + ESRmin 2
ESR = 0.022
Step 6: From Above Calculations Choose:
Co 233uF
ESR = 0.022
Step 7: Check the Ripple Current If Co can handle the ripple current you're done. Otherwise increase the output capacitance to handle the ripple current at maximum Vin and recheck the ESR using the equation for determining the actual output capacitance. If you are using tantalum or electrolytic capacitors you should increase the capacitance to the level of approaching the calculated ESR. If you are using poly capacitors a small resistor in series with the capacitor to bring the ESR to the desired level may be necessary for stability due to their low ESR values.
Where Fs is the switching frequency. Vout is the output voltage. Vinmin is the minimum input voltage. Vref is the SC1402 reference voltage. Rs is the sense resistor, (R9 on the EVAL board). Step 1: Determine the Crossover Frequency
Fc =
Fs Vout o ae 3 * c1+ e Vinmin
Fc = 64.516KHz
12 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000 If your ESR value varies significantly from the calculated value and you don't want to add more capacitance or add a series resistor in the capacitor path as described above. We recommend that you bench test the supply over temperature to verify transient response and operation of the SMPS.
Input Capacitor Selection
SC1402
Conversely: When the 3V output is at maximum ripple 1.5A (D = 50%), the 5V output adds 1.29A of ripple current. The worse case ripple current is then calculated by:
IRMS(MAX) = 1.5
2
+ 1.29
2
= 1.98A
Input capacitor is selected based upon the input ripple current demand of the converter. First determine the input ripple current expected and then choose a capacitor to meet that demand. The input RMS ripple current can be calculated as follows:
IRMS = VOUT * (VIN - VOUT ) * IOUT VIN
Clearly, the combined input capacitor bank must be chosen to handle 2A of ripple current under worstcase conditions.
MOSFET Switches
The worse case input RMS ripple current occurs at 50% duty cycle (D = 0.5 or Vin = 2 Vout) and therefore under this condition the IRMS ripple current can be approximated by:
IRMS = ILOAD 2
After selecting the voltage and current requirements of each MOSFET device for the upper and lower switches, the next step is to determine their power handling capability. For the EVAL board the IRF7413 met the voltage and current requirements. These are 30V, 9A FET's. Based on 850C ambient temperature, 1500C junction temperature and thermal resistance, their power handling is calculated as follows: Power Limit for Upper & Lower FET: TJ = 1500C; TA = 850C; ja = 50C/W
PT = TJ - TA 150 - 85 = = 1.3W 50 JA
Therefore, for a maximum load current of 3.0A , the input capacitors should be able to safely handle 1.5A of ripple current. For the EVAL board there are two such regulators that operate simultaneously. Each capable of 1.5A of ripple current, although it is impossible for both regulators to be at 50% duty cycle at the same time since they have different output voltages. For the EVAL board, we chose four 10uF, 30V OS-CON capacitors, two for each supply. Each capacitor has a ripple current capability of 1.38A at 100KHz, 45C. Following the capacitor-derating chart for temperature and frequency operation at 300KHz, two of these capacitors in parallel will suffice, as calculated below: The RMS ripple current is under a worst-case condition at full load, 3A each when both SMPSs are on. When the 5V output is at maximum ripple of 1.5A (D = 50%), the 3.3V output adds 1.41A of ripple current. The maximum ripple current is then calculated by:
IRMS(MAX) = 1.5 2 + 1.412 = 2.06A
Each FET must not exceed 1.3W of power dissipation. The conduction losses for the upper & lower FET can be determined. For the calculations below, a nominal input voltage of 12V, for Vout = 3.3V, Iout = 3A and f = 300KHz. The Rdson value for the upper & lower FET is 11m. We will calculate the conduction losses and switching losses for each FET. From the calculations below we are well within the 1.3W dissipation limit as calculated above. Conduction Losses Upper FET:
PCU = R DS * D * I2
PCU = 0.011 *
3.3 * 3 2 = 0.027W 12
Conduction Losses Lower FET:
PCL = R DS * (1 - D) * I2
3.3 o ae PCL = 0.011 * c 1 - * 3 2 = 0.072W 12 e
13 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
2A 3A IR IRF7413 Siliconix Si4412
SC1402
4A IR IRF7805 Siliconix Si4410
Switching Losses Upper FET:
2
High & Low IR IRF7901D1 Side FET's Siliconix Si4412 Input Capacitor Output Capacitor Resistor 10uF, 30V Sanyo OS-CON 330uF, 6.3V/10V* AVX TPS 0.033, Dale WSL2010-R033-F 15uF, Coilcraft DO-3316P-153
PSU =
CRSS * VIN * F * IOUT IG
=
240 * 10 -12 * 12 2 * 300000 * 3 = 0.031W 1
2 X 10uF, 30V Sanyo 3 X 10uF, 30V Sanyo OS-CON OS-CON 2X 330uF, 6.3V/10V* 4X 330uF, 6.3V/10V* AVX TPS AVX TPS 0.02, Dale WSL2010-R020-F 10uF, Coilcraft DO3316P-103 0.012, Dale WSL2512-R012-F 4.7uF, Coilcraft DO3316P-472
Note: switching losses exist on the upper FET only because the clamp diode across the lower FET will turn on prior to the lower FET turning on. Where Ig is the gate driver current. This is equal to 1A for the SC1402. Crss is the reverse transfer capacitance of the FET; in this case it equals 240pF for the IRF7413. So the total FET losses equate to: PFETS = 0.027+0.072+0.031 = 0.130W Note that as Vin increases the power dissipation from switching losses will also increase. This is especially important if the input to the supply is from an AC adapter. Therefore, it is necessary to check the calculations with your maximum input voltage specification. In addition, the distribution of power in the upper and lower FET will change as input voltage increases. Other losses to consider are gate charge losses, inductor switching and copper losses, and losses in the input and output capacitors. All these items will decrease efficiency and need to be carefully analyzed to obtain the highest efficiency possible, especially if running off battery power.
Basic Application Circuit
Inductor
*10V for 5V SMPS, 6.3V for 3V SMPS
Table 3
The basic dual-output 3.3V / 5V synchronous buck converter is shown in Figure 2. This circuit shows the minimum requirements for successful operation. For varying current levels, Table 3 provides a useful selection of components for varying supply requirements and is based on the calculations described previously. Input voltage ranges for all designs in the table are 6.5V to 28V. Frequency used in calculations is 300KHz.
14 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
PCB Layout
As with any high frequency switching regulator it is advisable to practice a careful layout strategy. This includes keeping loop area as small as possible. Properly decoupling lines that pull large amounts of current in short periods of time. To keep loop area small always use a ground plane and if possible split the plane in two areas, signal GND and power GND then tie the two together at one point. Be sure that high current paths have low inductance by making track widths wide where possible. We recommend the following layout for the SC1042 shown below. This layout has been optimized for having tight loop areas and bypassing the SC1402 properly.
15 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
EVALUATION BOARD SCHEMATIC
VIN
1
VIN
10U,30V C1 C2
R1 10
GND
1
D1 CMPSH-3A
C7 C8 0.22
+
+
10U,30V
C3
C4
10U,30V
+
+
10U,30V
VDD VDD
1
GND
1
GND
4.7U,35V
C5
4.7U,6.3V
C6 0.1 C12 0.1 C13 0.01
1
VL VL
1
OPEN
22
C9
21
VDD
C15
OPEN
C
A
D3
C10 0.1
C11 0.01
25 BST3 DH3
U1
4.7U,16V
+12V JU2
1
V+
VL
12OUT VDD BST5 DH5 LX5 DL5 PGND
4 5 18 16 17 19 20 14 13 330U,10V 12 15 9 6 11 R10 10.7K A
Q1
IR7413
10 9
VL CMPD2838 D9
C16 0.1
C 26 LX3 DL3
0.1
Q2
IR7413 C
7
27
C17
A
MBRS1100 C D4 C31 0.1uF
C14
2.2U,25V
RAW15V
1
T2/L2
3
L1 10uH
D5 140T3
SC1402ISS
2 1
Q3
IR7413
24
Q4
IR7413
D6 140T3
A
C28 0.1uF R23 301K
TTI5870
R8 .02
1
+5V
2
A
1
R20 +3.3V
1 C 330U,10V OPEN
C26 0.1uF
CSH3 CSL3
5 4 3
R9 .02
2
CSH5 CSL5 FB5 SEQ REF SYNC RESET GND
+5V
C
+5V
D7 140T3
301K
R11 3.32K 330U,10V
1
OPEN
FB3 PSAVE SHDN TIME/ON5 RUN/ON3
D8 140T3
C18
C19
C20
C21
C22
C23
10 23 7 28
OPEN
3
GND
1
1
1
JP5
JP3
1
JP4
GND
A
1
REF
GND
1
R13 10.7K
JU9
C27 100pF
R17 2M R16 2M R15 2M
C29 VL
R18 100K
2
2
2
R14 2M
C24 0.01
C30 0.1uF
100pF
JU7
R12 10.7K
REF REF
1
C25
4.7U,16V
SHDN
1
8
SYNC ON5
1 1k 2 R19 1
JP6
1
GND
1
ON3
1
RESET
1 4 3 2 1
PSAVE
1
S1 SW DIP-4
5 6 7 8 Title
SC1402 Eval Board
Size Document Number Rev
VIN
VL
B
Date:
RTP00005
Thursday, April 13, 2000
Sheet
E
1
of
1
16 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
4.96
SC1402
5V LINE REGULATION
3.29
3.3V LINE REGULATION
4.95 OUTPUT VOLTAGE (V)
3.28 OUTPUT VOLTAGE (V)
4.94
3.27
4.93
3.26
4.92
3.25
4.91
5
7.5
10
12.5
15
17.5
20
22.5
25
27.5
30
3.24
5
7.5
10
12.5
15
Vini INPUT VOLTAGE (V)
17.5 20 Vini INPUT VOLTAGE (V)
22.5
25
27.5
30
ILOAD = 0.5A ILOAD = 1A ILOAD = 3A
ILOAD = 0.5A ILOAD = 1A ILOAD = 3A
5V LOAD REGULATION
3.29 3.284 3.278 3.271
j 3.265
4.96 4.954 4.948 OUTPUT VOLTAGE (V) 4.941 4.935 4.929 4.923 4.916 4.91
3.3V LOAD REGULATION
OUTPUT VOLTAGE (V)
3.259 3.253 3.246 3.24
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
Iout ,Iout2 j i LOAD CURRENT (A)
Iout , Ioutj i LOAD CURRENT (A)
VIN = 15V VIN = 6V
VIN= 15V VIN = 6V
100 95 90 85 80 75 EFFICIENCY (%) 70 65 60 55 50 45 40 35
EFFICIENCY vs. 5V LOAD CURRENT
10 0 95 90 85 80 75 EFFICIENCY (%) 70 65 60 55 50 45 40 35 30
EFFICIENCY vs. 3.3V LOAD CURRENT
30
0 .1 Io uti , Io u t2j 5 V LOAD CURRENT (A)
1
10
30
0 .1 Io u ti , Io u t2j 3 V LOAD CURRENT (A)
1
10
VIN = 15V VIN = 6V
VIN = 15V VIN = 6V
17 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
Multi-Output, Low-Noise Power Supply Controller for Notebook Computers
December 15, 2000
SC1402
OUTLINE DRAWING - SSOP-28
Ref. MO-150AH
ECN00-1004
18 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

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